Halbleiter17
Intel is considering a return to memory technology decades after abandoning mainstream DRAM and, more recently, selling its NAND business.
●●●●●semiwikivor 5 h
Fabricated 22FDX ASIC achieves 3x area and power reduction for massive MU-MIMO-OFDM detection.
●●●●●arxiv-cs-arvor 14 h
Micron announces $10B research hub in Boise
●●●●●hn-topvor 14 h
Benchmarks analyze AMD EPYC 9005 memory scaling performance from four to twenty-four DDR5 RDIMMs.
●●●●●phoronixvor 2 d
Cerebras has a new wafer scale chip and a new box to put it in.
●●●●●yt-techtechpotatovor 2 d
AMD acquires Taalas, a company building chips with a single AI model wired directly into metal layers.
●●●●●yt-techtechpotatovor 14 d
NVIDIA published a whitepaper on Vera, an 88-core monolithic Arm v9.2 server CPU with 164 MB shared cache and 1.2 TB/s memory bandwidth.
●●●●●chipsandcheesevor 15 d
Hello you fine Internet folks, Today we are talking about one of the stranger x86 stories I have seen in a while.
●●●●●chipsandcheesevor 21 d
Patch adds support for RISC-V Second-stage page tables used by the IOMMU iohgatp register with specific bit coverage details.
●●●●●lore-riscvvor 4 h
Study proposes a stacked ensemble framework for early estimation of MBIST area and test time overhead in heterogeneous memory IPs.
●●●●●arxiv-cs-arvor 14 h
Paper proposes an exact multistate reliability framework for HBM systems with arbitrary finite bandwidth states.
●●●●●arxiv-cs-arvor 14 h
New RISC-V IOMMU PMU driver adds filtering support for device and process IDs with runtime counter detection.
●●●●●lore-riscvvor 15 h
Patch series implements RISC-V IOMMU hardware performance monitor support via an auxiliary device driver.
●●●●●lore-riscvvor 15 h
Siemens EDA updated Questa One with AI-infused tools for SoC, 3D IC, and chiplet verification at DAC 2026.
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Article states that semiconductor engineering is expanding from individual design tasks toward increasingly complete system analysis using multiphysics simulation.
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AI at the edge is already here, running on the devices all around you, no data center required.
●●●●●yt-techtechpotatovor 9 d
Arm’s 5-series cores are meant for tasks where performance barely matters, but power and area efficiency are top priorities.
●●●●●chipsandcheesevor 18 d
KI & Modelle8
A new resource-efficient ASIC integrates a quantized CNN inference engine for real-time EEG-based auditory attention decoding.
●●●●●arxiv-cs-arvor 14 h
HYDRA framework explores design space for heterogeneous chiplet architectures serving dynamic hybrid LLM workloads.
●●●●●arxiv-cs-arvor 14 h
Stealing Reasoning Traces from Proprietary LLM APIs A vanity domain name ( stolen-thoughts.com ) for a neat paper : Anthropic, OpenAI, and Google return encrypted chain-of-thought blocks to clients th
●●●●●simonwillisonvor 9 d
Researchers built a prototype self-sustaining AI virus that uses compromised GPU resources to run inference and infect more hosts.
●●●●●importaivor 18 d
Consolidation has been one of the paths that many astute observers predicted for the near-future of labs training models.
●●●●●interconnectsvor 19 d
Qwen 3.8 27B is an Apache 2 licensed vision-capable LLM with self-reported benchmarks showing a boost from predecessors.
●●●●●simonwillisonvor 4 d
Z.ai announced GLM-5.3, a coding model surpassing Kimi K3 and some Claude or GPT variants on benchmarks, soon available via API and Hugging Face.
●●●●●interconnectsvor 6 d
DeepSeek V4 Pro model weights are now available on Hugging Face with 1.7T parameters and 893 GB size.
●●●●●simonwillisonvor 8 d
Code, Kernel, Releases8
Linux 7.3 networking maintainers report being completely overwhelmed by code churn from AI and LLM agent outputs.
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Linux 7.3 merges AMD low-power core type handling and unifies Intel and AMD CPU core type handling.
●●●●●phoronixvor 2 d
Mojo programming language compiler and toolchain released under Apache 2 license, shifting from original Python superset goal.
●●●●●simonwillisonvor 2 d
This patch enables VFIO support on RISC-V architecture now that the IOMMU driver reports the required cache coherency capability.
●●●●●lore-riscvvor 20 h
Patch enables IOMMU_DMA for 64-bit RISC-V now that the driver supports MSI remapping.
●●●●●lore-riscvvor 20 h
Guest Linux uses mm_cpumask to decide whether an sfence.vma needs to be local or remote.
●●●●●lore-riscvvor 4 d
A RISC-V patch adds a SiFive MAL-9092 errata workaround for memory ordering in hypervisor instructions.
●●●●●lore-riscvvor 4 d
vLLM v0.27.0 adds Kimi K3 support, new Qwen and K-EXAONE models, and features like DeepGEMM support and compressed-tensors quantized checkpoints.
●●●●●gh-vllmvor 10 d